? semiconductor components industries, llc, 2003 october, 2003 ? rev. 4 1 publication order number: ntb125n02r/d ntb125n02r, ntp125n02r power mosfet 125 a, 24 v n-channel to-220, d 2 pak features ? planar hd3e process for fast switching performance ? body diode for low t rr and q rr and optimized for synchronous operation ? low c iss to minimize driver loss ? optimized q gd and r ds(on) for shoot?through protection ? low gate charge maximum ratings (t j = 25 c unless otherwise specified) parameter symbol value unit drain?to?source voltage v dss 24 v dc gate?to?source voltage ? continuous v gs 20 v dc thermal resistance ? junction?to?case total power dissipation @ t c = 25 c drain current ? continuous @ t c = 25 c, chip continuous @ t c = 25 c, limited by package continuous @ t a = 25 c, limited by wires single pulse (t p = 10 s) r jc p d i d i d i d i d 1.1 113.6 125 120.5 95 250 c/w w a a a a thermal resistance ? junction?to?ambient (note 1) total power dissipation @ t a = 25 c drain current ? continuous @ t a = 25 c r ja p d i d 46 2.72 18.6 c/w w a thermal resistance ? junction?to?ambient (note 2) total power dissipation @ t a = 25 c drain current ? continuous @ t a = 25 c r ja p d i d 63 1.98 15.9 c/w w a operating and storage temperature range t j , t stg ?55 to 150 c single pulse drain?to?source avalanche energy ? starting t j = 25 c (v dd = 50 v dc , v gs = 10 v dc , i l = 15.5 a pk , l = 1 mh, r g = 25 ) e as 120 mj maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c 1. when surface mounted to an fr4 board using 1 inch pad size, (cu area 1.127 in 2 ). 2. when surface mounted to an fr4 board using minimum recommended pad size, (cu area 0.412 in 2 ). pin assignment pin function 1 gate 2 drain 3 source 4 drain http://onsemi.com device package shipping 2 ordering information ntp125n02r to?220ab 50 units/rail ntb125n02r d 2 pak to?220ab case 221a style 5 50 units/rail 125 amperes, 24 volts r ds(on) = 3.7 m (typ) marking diagrams 125n2 = specific device code y = year ww = work week ntb125n02rt4 d 2 pak 800/tape & reel d 2 pak case 418aa style 2 d s g yww 125n2 yww 125n2r 1 2 3 4 1 2 3 4 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
ntb125n02r, ntp125n02r http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise specified) characteristics symbol min typ max unit off characteristics drain?to?source breakdown voltage (note 3) (v gs = 0 v dc , i d = 250 a dc ) temperature coefficient (positive) v (br)dss 25 ? 28 15 ? ? v dc mv/ c zero gate voltage drain current (v ds = 20 v dc , v gs = 0 v dc ) (v ds = 20 v dc , v gs = 0 v dc , t j = 125 c) i dss ? ? ? ? 1.5 10 a dc gate?body leakage current (v gs = 20 v dc , v ds = 0 v dc ) i gss ? ? 100 na dc on characteristics (note 3) gate threshold voltage (note 3) (v ds = v gs , i d = 250 a dc ) threshold temperature coefficient (negative) v gs(th) 1.0 ? 1.5 5.0 2.0 ? v dc mv/ c static drain?to?source on?resistance (note 3) (v gs = 10 v dc , i d = 110 a dc ) (v gs = 4.5 v dc , i d = 55 a dc ) (v gs = 10 v dc , i d = 20 a dc ) (v gs = 4.5 v dc , i d = 20 a dc ) r ds(on) ? ? ? ? 3.7 4.9 3.7 4.7 ? ? 4.6 6.2 m forward transconductance (note 3) (v ds = 10 v dc , i d = 15 a dc ) g fs ? 44 ? mhos dynamic characteristics input capacitance c iss ? 2710 3440 pf output capacitance (v ds = 20 v dc , v gs = 0 v, f = 1 mhz) c oss ? 1105 1670 transfer capacitance ( ds dc , gs ,) c rss ? 227 640 switching characteristics (note 4) turn?on delay time t d(on) ? 11 22 ns rise time ( v gs = 10 v dc , v dd = 10 v dc , t r ? 39 80 turn?off delay time (v gs = 10 v d c , v dd = 10 v d c , i d = 40 a dc , r g = 3 ) t d(off) ? 27 40 fall time tf ? 21 40 gate charge q t ? 23.6 28 nc (v gs = 4.5 v dc , i d = 40 a dc , v ds = 10 v dc ) ( note 3 ) q 1 ? 5.1 ? v ds = 10 v d c ) (note 3) q 2 ? 11 ? source?drain diode characteristics forward on?volta g e (i s = 20 a dc , v gs = 0 v dc ) (note 3) v s d ? 0.82 1.2 v dc forward on?voltage (i s = 20 a d c , v gs = 0 v d c ) (note 3) (i s = 55 a dc , v gs = 0 v dc ) (i 20 a v 0v t 125 c) v sd ? ? 0 . 82 0.99 065 1 . 2 ? v d c ( s dc , gs dc ) (i s = 20 a dc , v gs = 0 v dc , t j = 125 c) ? 0.65 ? reverse recovery time t rr ? 36.5 ? ns (i s = 30 a dc , v gs = 0 v dc , t a ? 17.7 ? (i s = 30 a d c , v gs = 0 v d c , di s /dt = 100 a/ s) (note 3) t b ? 18.8 ? reverse recovery stored charge q rr ? 0.024 ? c 3. pulse test: pulse width 300 s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperatures.
ntb125n02r, ntp125n02r http://onsemi.com 3 4.0 v 1.8 1.6 1.2 1.4 1.0 0.8 0.6 10 1000 100,000 010 120 4 2 v ds , drain?to?source voltage (volts) i d , drain current (amps) 0 v gs , gate?to?source voltage (volts) figure 1. on?region characteristics figure 2. transfer characteristics i d , drain current (amps) 0 0.006 160 120 80 0.004 0.002 40 200 figure 3. on?resistance versus drain current and temperature i d , drain current (amps) figure 4. on?resistance versus drain current and temperature i d , drain current (amps) r ds(on) , drain?to?source resistance ( w ) r ds(on) , drain?to?source resistance ( w ) figure 5. on?resistance variation with temperature t j , junction temperature ( c) figure 6. drain?to?source leakage current versus voltage v ds , drain?to?source voltage (volts) r ds(on) , drain?to?source resistance (normalized) i dss , leakage (na) 200 ?50 50 25 0 ?25 75 125 100 0 1.6 0.8 016 12 8.0 24 4.0 6 80 40 160 v ds 10 v t j = 25 c t j = ?55 c t j = 125 c t j = 125 c v gs = 10 v v gs = 4.5 v 150 v gs = 0 v i d = 55 a v gs = 4.5 v 0.008 0.01 0.008 0.006 0.002 0.01 t j = 25 c t j = ?55 c t j = 125 c t j = 150 c t j = 100 c t j = 125 c 120 0 200 80 40 160 2.4 3.2 4.0 0.004 0 160 120 80 40 200 v gs = 2.5 v t j = 25 c t j = ?55 c 20 100 8 3.0 v 10 v 3.5 v 4.5 v 5.0 v 6.0 v 8.0 v 10,000
ntb125n02r, ntp125n02r http://onsemi.com 4 r ds(on) limit thermal limit package limit v gs 1000 100 10 1.0 1000 10 10 8.0 6.0 4.0 2.0 0 60 50 40 30 0 10 7000 6000 10 5000 15 5 020 gate?to?source or drain?to?source voltage (volts) c, capacitance (pf) 4000 3000 2000 1000 0 5 q g , total gate charge (nc) figure 7. capacitance variation figure 8. gate?to?source and drain?to?source voltage versus total charge v gs , gate?to?source voltage (volts) figure 9. resistive switching time variation versus gate resistance r g , gate resistance ( w ) figure 10. diode forward voltage versus current v sd , source?to?drain voltage (volts) i s , source current (amps) t, time (ns) figure 11. maximum rated forward biased safe operating area v ds , drain?to?source voltage (volts) i d , drain current (amps) 02432 16 848 1 10 100 0 0.4 0.8 0.2 1.0 0.1 10 100 1.0 i d = 40 a t j = 25 c v gs v gs = 0 v v ds = 0 v t j = 25 c c rss c iss c oss c rss 20 10 0.6 c iss v gs = 20 v single pulse t c = 25 c v ds = 10 v i d = 40 a v gs = 10 v v gs = 0 v t j = 25 c 10 ms 1 ms dc t r t d(off) t d(on) t f v ds q 2 q 1 q t 40 100 100 s
ntb125n02r, ntp125n02r http://onsemi.com 5 1 0.1 0.01 0.00001 1 0.1 0.01 0.001 0.0001 10 r(t), effective transient thermal response (normalized) t, time (s) normalized to r q jc at steady state figure 12. thermal response package dimensions to?220ab case 221a?09 issue aa notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension z defines a zone where all body and lead irregularities are allowed. dim min max min max millimeters inches a 0.570 0.620 14.48 15.75 b 0.380 0.405 9.66 10.28 c 0.160 0.190 4.07 4.82 d 0.025 0.035 0.64 0.88 f 0.142 0.147 3.61 3.73 g 0.095 0.105 2.42 2.66 h 0.110 0.155 2.80 3.93 j 0.018 0.025 0.46 0.64 k 0.500 0.562 12.70 14.27 l 0.045 0.060 1.15 1.52 n 0.190 0.210 4.83 5.33 q 0.100 0.120 2.54 3.04 r 0.080 0.110 2.04 2.79 s 0.045 0.055 1.15 1.39 t 0.235 0.255 5.97 6.47 u 0.000 0.050 0.00 1.27 v 0.045 --- 1.15 --- z --- 0.080 --- 2.04 b q h z l v g n a k f 123 4 d seating plane ?t? c s t u r j style 5: pin 1. gate 2. drain 3. source 4. drain
ntb125n02r, ntp125n02r http://onsemi.com 6 package dimensions d 2 pak case 418aa?01 issue o style 2: pin 1. gate 2. drain 3. source 4. drain seating plane s g d ?t? m 0.13 (0.005) t 23 1 4 3 pl k j v e c a dim min max min max millimeters inches a 0.340 0.380 8.64 9.65 b 0.380 0.405 9.65 10.29 c 0.160 0.190 4.06 4.83 d 0.020 0.036 0.51 0.92 e 0.045 0.055 1.14 1.40 g 0.100 bsc 2.54 bsc j 0.018 0.025 0.46 0.64 k 0.090 0.110 2.29 2.79 s 0.575 0.625 14.60 15.88 v 0.045 0.055 1.14 1.40 ?b? m b w w notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. f 0.310 ??? 7.87 ??? m 0.280 ??? 7.11 ??? m f m f m f variable configuration zone u view w?w view w?w view w?w 123 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 ntb125n02r/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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